The present invention relates generally to integrated circuit pad circuits, and more particularly to controlling the slew rate of output drivers using external resistance and programmed delays.
Integrated circuits communicate with one another using digital signals. In the digital world, a digital signal may be in one of a plurality of predefined quantized states. Because digital signals are transmitted using an analog signal along a transmission line, the predefined quantized states of the digital signal are represented by different ranges of voltages within the total voltage range of the signal. For example, a typical digital integrated circuit (IC) based on a binary system will communicate using two statesxe2x80x94zero (xe2x80x9c0xe2x80x9d) and one (xe2x80x9c1xe2x80x9d). The digital state of xe2x80x9c0xe2x80x9d is represented by the range of voltages between a minimum voltage VMIN (e.g., 0 volts) of the potential voltage range of the signal and a voltage VLOW that is low relative to the total range of voltage, whereas the digital state of xe2x80x9c1xe2x80x9d is represented by the range of voltages between a voltage VHIGH that is high relative to the total range of voltages and a maximum voltage VMAX (e.g., 1.5 volts) of the potential voltage range of the signal. In binary system example, the state of the digital signal is unknown when the voltage level of the signal is between VLOW and VHIGH, which typically only occurs during transitions of the signal from either the xe2x80x9c0xe2x80x9d state to the xe2x80x9c1xe2x80x9d state or vice versa.
Because the transmission signal is actually analog, the transition between digital states does not occur instantaneously, but instead occurs over a period of time TTRANSITION that is dependent on the physical conditions present on the transmission line. It is well known that signal transitions over a transmission line will suffer a delay known as a propagation delay due to the parasitic resistance, inductance, and capacitance of the line. This delay increases with the length of the line. In addition, it is also well-known that unless the impedance of the transmission line matches that of the load it drives, the signal will degrade because the mismatch in impedance leads to reflections from the load that are passed back to the driver circuit, which may then be re-reflected causing further signal degradation.
Furthermore, when the driver circuit drives multiple loads with differing impedances, the transmission line requires multiple stubs to properly match each of the loads during realtime operation. However, the use of multiple stubs then generates multiple reflections. One way of ensuring proper detection of signal states is to control the edge rates of the signal.
However, this competes with the trend towards ever increasing signal frequencies, which results in higher edge rates. Accordingly, a need exists for a technique for controlling the slew rate of signal edge transitions without sacrificing the signal frequency.
The present invention is a method and circuit for controlling the slew rate of integrated circuit output drivers by controlling the resistance of a pre-driver circuit that generates the drive signal.
In particular, the present invention allows the ability to vary the slew rate of the signal on the output pad by controlling the current flow through a set of pre-driver FETs that driver the output stage FETs. In a preferred embodiment, this is accomplished using a programmable resistance pre-driver circuit to drive the output stage of the output driver. The slope of the pre-driver signal driving the output stage FETs is controllable by varying the source resistance of the pre-driver FETs.
In addition to controlling the slew rate of the output signal, the use of the programmable resistance pre-driver circuit may also be advantageous to overcome chip-to-chip parameter differences due to variations in voltage, temperature, and manufacturing process.
For even slower slew rate requirements, the invention may also implement a staged turn-on of the output driver legs. This gives a slower possible output slew rate than possible with edge rate control of a single output driver leg alone.